vProto - utilizes a human-perceptible State Machine and generates C++ code based on it to facilitate state transitions when parsing incoming data. It's extremely convenient for parsing existing protocols as well as describing custom ones. It's designed to work with any data fragmentation (data can arrive even byte by byte), which is highly relevant for the TCP protocol.


vSyn - transfer (translator) C language to Verilog. The development of algorithms in the C language is significantly simpler, more compact, and faster than in hardware description languages (Verilog, VHDL, SystemC, etc).

An automated process of transferring C logic to the hardware level is a highly effective approach in implementing complex and large projects on PLDs (Programmable Logic Devices) FPGA:

  • Time savings on development, testing, and debugging (C code is much easier to debug on x86/64)
  • Automated process of forming state machines (Finite State machine)
  • Memory interface compatible with the Memory Interface Generator (LogiCORE IP Core from Xilinx)
  • Minimization of code size and consequently, reduction of errors
  • Ability to not worry about the complexities of Verilog internals
  • Code portability, ability to use a replenishable algorithm library: red-black-tree (std::map)
On this website, you can try out this technology for free and without registration here.


vSwitch is a hardware solution that allows FPGA-based packet management in Ethernet 10GBase-T/1000Base-T/100Base-T networks. Package management is carried out using FPGA, enabling operation at channel speed without packet loss.

  • Support for 10Gbit/s, 1Gbit/s, 100Mbit/s
  • Low power consumption
  • Wide range of applications


A Red-Black Tree (RB-Tree) is an algorithm for an associative array (stl::map).It is one of the self-balancing binary search trees, ensuring logarithmic growth in tree height relative to the number of nodes (N) and quickly performing basic tree operations: addition, removal and search.

An example translation using vSyn from C code to Verilog is provided.The interface is compatible with the Memory Interface Generator (LogiCORE IP Core from Xilinx) for working with RAM.


Tetris-3D is one of my first working programs with multiplayer capability. It has a size of 24 kilobytes (developed in assembly) using OpenGL.

Author: Shchekoldin Sergey (Щеколдин Сергей)